The world’s first multi-array memristor memory-computing integrated system is on the market, Made in China

Growing demand for computing and storage

integrated circuit chip technology

Facing many new challenges

Tsinghua University Qian He, Wu Huaqiang team, etc.

Cooperative research and development

Memory-Computer Integrated System Based on Multiple Memristor Arrays

Energy Efficiency When Processing Convolutional Neural Networks

Two orders of magnitude higher than graphics processor chips

Significantly increased the computing power of computing equipment

successfully achieved with less power consumption

and lower hardware cost

complete complex calculations

Related results have recently been

Published online in Nature

Recently, the team of Professor Qian He and Wu Huaqiang from the Institute of Microelectronics of Tsinghua University and the Future Chip Technology Advanced Innovation Center and their collaborators published a research paper entitled “Fully hardware-implemented memristor convolutional neural network” online in “Nature”, reporting A complete hardware implementation of a convolutional network based on a memristor array chip is presented. The memory-computing integrated system based on multiple memristor arrays developed by this achievement is two orders of magnitude higher in energy efficiency than graphics processor chips (GPU) when processing convolutional neural networks (CNNs), which greatly improves the computing power of computing devices. It has successfully realized the completion of complex calculations with less power consumption and lower hardware cost.

The world’s first multi-array memristor memory-computing integrated system is on the market, Made in China

Schematic diagram of multiple memristor array chips working together. Based on the memristor array, parallel computing based on the laws of physics (Ohm’s law and Kirchhoff’s law) can be realized, and the integration of storage and computing can be realized at the same time, breaking the limitation of computing power by the “Von Neumann bottleneck”.

The world’s first multi-array memristor memory-computing integrated system is on the market, Made in China

Memory and computing integrated system based on memristor chip

With the continuous improvement of computing and storage requirements for artificial intelligence applications, integrated circuit chip technology faces many new challenges. On the one hand, with the slowdown of Moore’s Law, it is becoming more and more difficult to obtain computing power improvement through integrated circuit process scaling. On the other hand, in the traditional “von Neumann” architecture, computing and storage are completed in different circuit units , which will result in increased power consumption and extra latency for large data transfers. In January 2020, Alibaba Dharma Academy released the “Top Ten Technology Trends in 2020” report, of which the second major trend is “computation and storage integration to break through the bottleneck of AI computing power”. The report pointed out: “The integration of data storage units and computing units can significantly reduce data handling and greatly improve computing parallelism and energy efficiency. The innovation of computing and storage integration in hardware architecture will break through the bottleneck of AI computing power.” The new memory-computing integrated architecture based on memristor can use Ohm’s law and Kirchhoff’s current law to realize in-situ computing (Compute on Physics) based on the laws of physics, breaking the computational bottleneck problem in the “von Neumann” architecture , to meet the high demand for computing hardware for complex tasks such as artificial intelligence.

The current international related research is still stuck in the verification of simple network structure, or the simulation based on a small amount of device data. There are still many challenges in the complete hardware implementation based on memristor array: Resistor arrays are still a challenge; in terms of systems, the inherent non-ideal characteristics of devices (such as inter-device fluctuations, device conductance stuck, conductance state drift, etc.) On the one hand, the realization of the convolution function of the memristor array requires continuous sampling and calculation of multiple input blocks in a serial sliding manner, which cannot match the computational efficiency of the fully connected structure.

The team of Professor Qian He and Wu Huaqiang successfully fabricated a high-performance memristor array by optimizing the material and device structure. In order to solve the problem of the system recognition accuracy decline caused by the non-ideal characteristics of the device, a new hybrid training algorithm is proposed, which only needs to train the neural network with fewer image samples, and fine-tune some of the weights of the last layer of the network to save the calculation. The recognition accuracy of the integrated architecture on the handwritten digit set reaches 96.19%, which is comparable to the recognition accuracy of the software. At the same time, a spatial parallel mechanism is proposed to program the same convolution kernel into multiple groups of memristor arrays. Each group of memristor arrays can process different convolution input blocks in parallel, increasing the degree of parallelism to speed up the convolution calculation. . On this basis, the team built a complete storage and computing integrated system composed of all hardware, integrated multiple memristor arrays in the system, and efficiently ran the convolutional neural network algorithm on the system, successfully verifying image recognition. This function proves the feasibility of the full hardware implementation of the storage-computing integrated architecture.

The world’s first multi-array memristor memory-computing integrated system is on the market, Made in China

Storage and Computing Integrated System Architecture

In recent years, the team of Professors Qian He and Wu Huaqiang has long been devoted to the research on the integrated storage and computing technology for artificial intelligence, and has achieved innovative breakthroughs at multiple levels such as device performance optimization, process integration, circuit design, architecture and algorithms, and successively published in “Nature Communications”. Published many papers in top academic conferences such as International Electronic Devices Conference (IEDM) and International Solid State semiconductor Circuits Conference (ISSCC) in journals such as Nature Communications, Nature Electronics, Advanced Materials, etc. .

Team photo

Professor Wu Huaqiang from the Institute of Microelectronics of Tsinghua University is the corresponding author of this paper, and Yao Peng, a doctoral student of the Institute of Microelectronics of Tsinghua University, is the first author. The research work was supported by the National Natural Science Foundation of China, the National Key R&D Program, the Beijing Municipal Science and Technology Commission, the Beijing National Research Center for Information Science and Technology, and Huawei Technologies Co., Ltd.

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