*frequency shift keying* (FSK) and*phase shift keying* (PSK) modulation schemes are widely used in digital communications, radar, RFID, and many other applications. The simplest FSK uses two discrete frequencies to transmit binary information, where a logic 1 represents the mark frequency and a logic 0 represents the space frequency. The simplest PSK is binary (BPSK), using two phases 180° apart. Figure 1 shows these two modulation methods.

**Figure 1. Binary FSK (a) and PSK (b) modulation.**

*direct digital frequency synthesizer*(DDS)’s modulated output enables frequency and/or phase switching in either a phase-continuous or phase-coherent manner (as shown in Figure 1, see also “Phase-Coherent FSK Modulation with Multichannel DDS,”), making DDS technology an FSK and Ideal for both modulation methods of PSK.

This article will describe how to implement a zero-crossing FSK or PSK modulator using two simultaneous DDS channels. Here, we will utilize the AD9958 dual, 500 MSPS, pure DDS (see appendix) to achieve zero-crossover switching frequency or phase, but any dual synchronous solution should do the trick. In phase-coherent radar systems, zero-crossing switching can reduce the amount of post-processing required for target feature recognition, and spectral scatter can be reduced at zero-crossing PSK.

Although the two outputs of the AD9958 DDS channel are independent of each other, they share an internal system clock and are on the same silicon die, so they are more reliable than the outputs of multiple single-channel devices that are synchronized when temperature and power supply changes inter-channel consistency. In addition, the process variability that may exist between different devices is also greater than the process variability between two channels on the same silicon wafer, thus making multi-channel DDS the first choice for zero-crossing FSK or PSK modulators.

**Figure 2. Setup of a zero-crossing FSK or PSK modulator.**

A key element of any DDS is the phase accumulator, which in this scheme is 32 bits wide. When the accumulator overflows, any remaining value is retained. When the accumulator overflows with no remainder (see Figure 3), the output is exactly phase 0 and the DDS engine starts working from the value at time 0. The rate at which zero overflow occurs is called the full repetition rate (GRR) of the DDS.

**Figure 3. Basic DDS for accumulator overflow.**

GRR is determined by the rightmost non-zero bits of the DDS Frequency Tuning Word (FTW) and is calculated as follows:

*GRR* = *FS*/2*n*

in:

*FS*is the sampling frequency of the DDS.*n*is the rightmost non-zero bit of the FTW.

For example, suppose a DDS with a sampling frequency of 1 GHz uses 32-bit mark FTW and space FTW, and its binary value is as follows. At this point, the rightmost non-zero bit of one of the two FTWs is the 19th bit, so GRR = 1 GHz/219, or about 1907 Hz.

Mark (CH0) 00101010 00100110 10100000 00000000

Space number (CH0) 00111010 11110011 11000000 00000000

GRR (CH1) 00000000 00000000 00100000 00000000

The DDS itself switches the frequency in a phase-continuous manner. This means that when the frequency tuning word changes, there is no instantaneous phase change. That is, when the new FTW is valid, the accumulator will start accumulating the new FTW from its current phase. However, phase coherence requires an instantaneous transition to the phase of the new frequency, as if the new frequency always existed. Therefore, in order for standard DDS to achieve phase-coherent FSK frequency switching, the transformation from mark frequency to space frequency must be performed when both frequencies have the same absolute phase. To achieve zero-crossing switching in a phase-coherent manner, the DDS must perform frequency translation at 0 degrees (ie, when the accumulator’s overflow residual is zero). Therefore, we must determine the constant at which the phase-coherent zero-crossing occurs. If the GRRs of the mark and space FTWs are known, the smaller of the two GRRs (if different) is the desired phase-coherent zero-crossing point.

Three criteria must be followed when implementing phase-coherent zero-crossover switching:

- It must be possible to determine the smaller GRR of both the mark and space FTW associated with CHO in Figure 2.
- The second DDS channel (CH1 in Figure 2) must be synchronized to CH0 in Figure 2 with all but one bit in the FTW corresponding to the smaller GRR zero.
- It must be possible to use the inversion of the second channel to trigger a frequency shift on CH0 in Figure 2.

Unfortunately, the delay between when the DDS accumulator reaches zero and when zero phase appears at the output further complicates the solution. The good news is that this delay is constant. For an ideal solution, the auxiliary channel must be phase adjusted to compensate for this delay. Both channels of the AD9958 have a*Phase offset* word, which can be used to solve this problem.

The AD9958 dual DDS produces the results shown in Figure 4, Figure 5, and Figure 6. Figure 4 and Figure 5 show the relationship between phase-continuous FSK switching and zero-crossing FSK switching. Figure 5 shows both phase-continuous switching and phase-coherent switching. Figure 6 shows the results of a pseudorandom sequence (PRS) data stream switching between multiple frequencies.

**Figure 4. Phase-continuous FSK transition.**

**Figure 5. Zero-crossing FSK transition.**

**Figure 6. Zero crossings (multiple FSK transitions).**

The AD9958 dual-channel DDS produces the results shown in Figure 7 and Figure 8. These figures show the relationship between phase-continuous BPSK switching and zero-crossing BPSK switching.

**Figure 7. Phase-continuous BPSK conversion.**

**Figure 8. Zero-crossing BPSK transition.**

**appendix****Two-Channel, 10-Bit, 500 MSPS Direct Digital Synthesizer**

The AD9958 dual direct digital synthesizer (DDS) is a full-featured, built-in two 10-bit, 500 MSPS current output DACs, as shown in Figure 9. Both channels share a single system clock and are therefore inherently synchronized; additional encapsulation can be used when more than two channels are required. The frequency, phase, and amplitude of each channel can be independently controlled, allowing it to provide correction for system-dependent mismatches. These parameters can be swept linearly; or 16 levels can be selected for FSK, PSK or ASK modulation. The output sine wave can be tuned with 32-bit frequency resolution, 14-bit phase resolution, and 10-bit amplitude resolution. The AD9958 operates from a 1.8 V core supply, is logic compatible with 3.3 VI/O supply, and consumes 315 mW (all channels on) and 13 mW (shutdown mode). Specified over the –40°C to +85°C temperature range, it is available in a 56-pin LFCSP package and is priced at $20.24/piece in 1,000-piece quantities.

**Figure 9. AD9958 block diagram.**

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