“The semiconductor market is trending towards widespread adoption of silicon carbide (SiC) devices, including Schottky barrier diodes (SBDs) and power MOSFETs for industrial and automotive applications. At the same time, the long-term reliability of these devices has become a hot issue due to the limited field data available for analysis. Some SiC suppliers have started shipping SiC devices according to stringent industrial and automotive (AEC-Q101) standards, while others not only exceed the requirements of these standards, but also provide data for harsh environment endurance testing.In order to maintain high penetration of SiC devices in mission- and safety-critical applications, this
The trend in the semiconductor market is the widespread adoption of silicon carbide (SiC) devices, including Schottky barrier diodes (SBDs) and power MOSFETs for industrial and automotive applications. At the same time, the long-term reliability of these devices has become a hot issue due to the limited field data available for analysis. Some SiC suppliers have started shipping SiC devices according to stringent industrial and automotive (AEC-Q101) standards, while others not only go beyond these standards, but also provide data for harsh environment endurance testing. In order to maintain high penetration of SiC devices in mission- and safety-critical applications, it is critical that this and test strategy be combined with specific design rules to achieve high avalanche tolerance.
Rapidly growing market
The device market share is expected to accelerate over the next few years, mainly driven by the electrification of the transportation industry. SiC dies will be the basic building blocks in Modules for applications such as on-board chargers and powertrain traction systems. Due to the higher critical electric field for avalanche breakdown, high-voltage SiC devices have a much smaller form factor than comparable silicon devices and can operate at higher switching frequencies. The thermal performance of SiC is also very good. It not only has good heat dissipation performance, but also works at high temperatures. In practice, operating temperatures typically reach 175 °C and rarely exceed 200 °C, mainly limited to the assembly process (solder metal and encapsulation material). SiC devices are inherently more efficient than silicon devices, and switching to SiC dies can greatly reduce the number of individual dies in a module.
As SiC devices move from niche to mainstream, major challenges associated with mass production ramp-up are gradually being overcome. To ease this transition, fabs are building SiC production lines that can share tools with existing silicon production lines. This arrangement effectively reduces the cost of the SiC die, as it shares the overhead with the Si production line. Wafer supply constraints are no longer an issue as wafer suppliers ramp up their capacity significantly. Thanks to continuous improvements in 4H-SiC substrates and epitaxial growth, high-quality 6-inch wafers with extremely low crystalline defect density are now available. According to electrical parameter tests, the higher the wafer quality, the higher the yield of SiC devices.
It is important to remember, however, that since these devices have only been on the market for a few years, field reliability data is limited. In addition, SiC devices are much more difficult than silicon devices due to their own set of challenges. In SiC devices, the electric field under reverse bias conditions is nearly an order of magnitude higher. Such high electric fields can easily damage the gate oxide layer if proper design rules are not applied. The trap density near the SiC gate oxide interface is also much higher. As a result, instability may occur during burn-in testing due to the charged traps. Our focus has always been on improving long-term reliability, and the results are encouraging, with recent Display devices passing stringent industrial and automotive (AEC-Q101) standards.
In addition to this, SiC suppliers have also started to take the next step, which is to provide data for harsh environment endurance testing.
Harsh Environment Resistance Test
As an example, Microchip, through its subsidiary Microsemi, has performed harsh environment endurance tests on its SiC SBDs and MOSFETs for 700V, 1200V and 1700V voltage nodes. Tests have shown that a high level of Unclamped Inductive Switching (UIS) tolerance is critical for long-term reliability of the device. It is also shown that during UIS testing, high transient currents flow through the reverse-biased device and drive it into avalanche breakdown. Under the combined action of high current and high voltage, a large amount of heat is generated and the temperature rises sharply. The localized temperature of the durable power MOSFET can reach 500°C, well above the typical temperature rating.
The tolerance is closely related to the epitaxy quality and manufacturing process at the front and back end of the production line. Even tiny crystal defects in epitaxy or process-related defects can constitute a weak link, causing premature device failure during UIS testing. This explains why single-pulse and repetitive UIS (RUIS) testing should be included in a comprehensive analysis of product line tolerance.
The single-pulse test is used as a screening test to identify devices with lower UIS tolerance. In order to guarantee the UIS rating in the product data sheet, all devices should be tested before shipping to the customer. However, the device may experience multiple UIS events during field service. In order to analyze the characteristics of gradual wear, repeated tests are required. For in-depth characterization, a large number of pulses should be applied to the device, a common practice is 100,000 shocks.
During the UIS pulse, the current in the device under test decreases continuously, while the voltage remains essentially constant, but varies slightly due to thermal effects (Figure 1). The energy of the UIS pulse is defined by the current at the beginning of the pulse and the inductance of the load. During the test, the energy is adjusted by changing the inductance value. The current remains constant; it is equal to the forward current rating of the SBD, which is also equal to two-thirds of the drain current rating of the MOSFET.
Figure 1: RUIS test setup and current and voltage waveforms during UIS pulse
The test has specific constraints, the main purpose of which is to prevent temperature build-up from one pulse to the next. Before applying a new pulse, it is important to ensure that the device temperature is close to ambient temperature. In the test setup shown in Figure 1, a thermocouple sensor was used to monitor the temperature of the device, and the pulse repetition frequency was adjusted to obtain a constant reading. To help cool the device, it should be mounted on the heatsink just below the fan.
Device Design for High Avalanche Tolerance
In addition to employing an appropriate testing process, best-in-class UIS tolerance requires the use of the following set of design rules:
High-voltage terminations are designed to have an inherent breakdown voltage high enough to ensure that the active area goes into avalanche first. In this case, the energy is spread over the entire active area, rather than in the narrow termination, which can lead to premature failure.
Electric field shielding in the JFET region is critical to protect the gate oxide. The design and implantation scheme of the P-type doped well used to define the JFET region should be carefully optimized in order to provide adequate shielding without severely affecting the on-state resistance.
Utilizing passivation materials with high thermal conductivity provides a path for heat to dissipate through the top of the die.
Both Schottky diodes and power MOSFETs designed using these rules perform well in harsh environment endurance tests. Testing of the SBD continued until single-pulse and repetitive UIS failures, while also monitoring multiple DC parameters. The results of this test show that the forward voltage and reverse leakage current of the device are quite stable, while the reverse breakdown voltage increases slightly, which can be attributed to free carrier trapping near the upper surface of the SiC. The pulse energy just before failure is shown in Figure 2. UIS tolerance increases with device voltage rating. Given that most of the heat is generated in the epitaxial region, this trend is not difficult to explain. As the epitaxial thickness increases due to the increased voltage rating, the heat generated per unit volume decreases, which in turn reduces the temperature in the device. Tolerance to UIS is systematically reduced due to repeated testing, but to a small extent. Compared with single-pulse UIS, the difference is less than 10%. There is no strong additive effect of multiple UIS pulses, and the SBD is expected to maintain high tolerance during field commissioning.
Figure 2: Specific energy per active region before failure of 700V, 1200V and 1700V SiC SBDs
Harsh-environment endurance characterization should focus on the long-term reliability of the gate oxide, which does not require stressing the device to failure. Alternatively, a repetitive test consisting of 100,000 relatively low energy pulses can be used. As an example, Microsemi 1200V/40 mΩ MOSFETs are designed using avalanche tolerance rules, tested with 100 mJ pulses, and have a single-pulse UIS rating of 2.0J. Most DC parameters are unaffected; however, a modest increase in gate leakage is observed as this test stresses the gate oxide. To determine whether long-term reliability was compromised, we imposed a time-varying dielectric breakdown on the device. Figure 3 shows the failure time when 50 A DC is applied to the gate of various devices, including Microsemi SiC devices developed using the company’s avalanche tolerance rules, and devices from three other suppliers.
Figure 3: TDDB failure times for 1200V MOSFETs from four suppliers
The adoption of SiC devices in the industrial and automotive markets requires stringent long-term reliability requirements. The strategy to meet these requirements is to pass the product to the automotive AEC-Q101 standard and to characterize extreme environmental resistance tests that have not yet been standardized. It is also important to achieve high avalanche tolerance by applying design rules. When used together, these measures not only help ensure that SiC devices continue on the road to rapid adoption, but also provide the long-term reliability required for these applications.
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